Design And Analysis Of A 45nm Low-Power High-Stable Proposed 8t Sram Cell And Array

The goal of this project is to carry out the new Proposed 8T SRAM cell and also design the array memory of 8-row by the 8-column with technology of 45nm node. Suggested proposed technique to reduce the current of short circuit leakage for that purpose just increases the path resistance of circuit from Vdd to GND. To access the SRAM array there is a 3-to-8 decoder that uses 3-bit address lines. The SRAM cells have been optimised to run read-write operation at cycles 100 MHz frequency while taking less power and maintaining a sufficient static noise margin. Software simulations are used to create and configure both the decode and array of SRAM by using Cadence Virtuoso (ADE) tool. The HSNM increases by 12.42% and The WSNM increases by 18.13% when moving from a 6T to an 8T configuration. The Proposed 8T configuration exhibits a 24.06% decrease in read total power and slight decrease of 1.06% in write total power. It also achieves a 30.20% reduction in write dynamic leakage power and 40.43% reduction in read dynamic leakage power indicating better efficiency during dynamic operations. The recommended technique appears to have a better Static Noise margin and Power Consumption than the standard approach, based on the data.