Artificial intelligence (AI) and machine learning systems have demonstrated great efficacy in addressing diverse jobs including data analysis and precise prediction. Although these technologies offer benefits, they need substantial computational resources and can use a large amount of energy when executed on current processing units. The First Carbon Nanotube Tensor
A team of scientists from Peking University and other research institutions in China have recently created a highly promising tensor processing unit (TPU) using carbon nanotubes. This TPU has the potential to significantly improve the energy efficiency of running AI algorithms. The carbon nanotube-based tensor processing chip, which was detailed in an article published in Nature Electronics, has the potential to represent a significant advancement in the development of future chips.
“According to Zhiyong Zhang, one of the authors of the paper, we have effectively created the first-ever tensor processor chip (TPU) using carbon nanotubes, Our inspiration stemmed from the rapid advancement of AI applications and Google’s development of TPU.” From ChatGPT to Sora, the advent of artificial intelligence is bringing about a new era of transformation. However, the conventional silicon-based semiconductor technology is progressively inadequate in fulfilling the computational requirements of vast volumes of data. We have discovered a resolution in light of this worldwide predicament.
Systolic arrays, in the field of computer science, refer to networks of processors that perform rhythmic computations on data, enabling its unrestricted flow, analogous to the circulation of blood in the human body. Zhang and his colleagues devised a novel and effective systolic array architecture by utilizing carbon nanotube transistors, which are field effect transistors (FETs) with channels composed of carbon nanotubes rather than traditional semiconductors. Utilizing the aforementioned architecture, they successfully engineered the first-ever TPU composed of carbon nanotubes, as per the latest records.
“According to Zhang, the chip consists of 3,000 field-effect transistors made of carbon nanotubes. These transistors are arranged in 3*3 processing units (PEs).” The system consists of 9 processing elements (PEs) that are organized in a systolic array design. This architecture allows for concurrent execution of two-bit integer convolution and matrix multiplication operations.
Scanning electronic microscope image of a processing unit (PE). Credit: Nature Electronics (2024). DOI: 10.1038/s41928-024-01211-2.
Zhang and his colleagues developed a tightly connected design that facilitates the transmission of systolic input data. The data flow within the design minimizes the number of read and write operations performed on static random-access memory (SRAM) components, resulting in substantial energy conservation.
“According to Zhang, each processing element (PE) receives data from its upstream neighbors (located above and to the left), performs independent calculations to obtain a partial result, and then transmits this result to its downstream neighbors (located to the right and below).” “Each processing element (PE) is specifically designed to handle 2-bit multiply-accumulate (MAC) operations and perform matrix multiplication on both signed and unsigned integers.” The CNT TPU, when combined with systolic data flow, has the capability to enhance the speed of convolution operations in neural network applications.
The team’s suggested system architecture was meticulously crafted to expedite tensor operations executed by artificial neural networks, seamlessly transitioning between integer convolutions and matrix multiplications. The tensor processing chip they created using this design could serve as a significant breakthrough for the advancement of novel, high-performance integrated circuits built on low-dimensional electronics.
“Zhang stated that they developed a convolutional neural network with five layers using their carbon-based tensor processor chip. This network has achieved an accuracy rate of up to 88% in image recognition tasks. Additionally, it consumes only 295μW of power, which is the lowest among all recently developed convolutional acceleration hardware technologies.”
The system simulation findings demonstrate that the carbon-based transistor, utilizing the 180 nm technology node, achieves a frequency of 850 MHz and an energy efficiency beyond 1TOPS/w. This highlights clear benefits over alternative device technologies operating at the same technology node.
Systolic architecture of CNT TPU. Credit: Nature Electronics (2024). DOI: 10.1038/s41928-024-01211-2.
In summary, the researchers’ initial simulations and testing demonstrate the potential of their carbon-based TPU, indicating that it is very suitable for executing machine learning-based computational models. In the future, this chip has the potential to exhibit superior computational capabilities and enhanced energy efficiency compared to current semiconductor-based devices.
The endeavors of this research team have the potential to ultimately expedite the functioning of convolutional neural networks while simultaneously diminishing their energy usage. Meanwhile, Zhang and his colleagues intend to enhance the chip’s performance, energy efficiency, and scalability.
“Zhang suggested that the performance and energy efficiency of this technique could be improved by utilizing aligned semiconducting CNTs as channel materials, reducing the size of the transistor, increasing the number of bits of PEs, or implementing CMOS logic..
“The CNT TPU could also potentially be built in BEOL in a silicon fab for three-dimensional integration: that is, a silicon CPU at the bottom with a CNT TPU on top as a co-processor. Moreover, 3D monolithic integration of multilayer CNT FETs could be studied for potential advantages of reduced latency and more bandwidth.”
