Approximation computations have attracted much attention recently, especially in the context of signal processing. The computational power of image and video compression techniques such as JPEG, MPEG, and others, which is imperceptible to humans, makes them perfect candidates for approximation computation to be used to their advantage. Apart from the fact that the level of hardware approximation is fixed, current approximation designs are not data adaptive. For example, if an MPEG encoder is configured with a fixed hardware configuration for approximation, the output quality will vary significantly for different input videos (i.e., for a fixed approximation level). In this paper, we propose a reconfigurable MPEG encoder architecture that maximises power consumption while maintaining a certain peak signal-to-noise ratio (PSNR) threshold for each video. As a result, we create reconfigurable adder/subtractor blocks (RABs) that allow us to change the approximation level. We then use these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We recommend two methods for automatically adjusting the approximation degree of the RABs in these two modules during runtime. According to the experimental findings, by dynamically adjusting the level of hardware approximation in line with the input video, we may be able to save up to 38% more power compared to a normal non-approximated MPEG encoder design.
The proposed reconfigurable approximation architecture can easily be extended to various DSP applications, even if it is presented for the specific scenario of an MPEG encoder.
2 comments